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Freescale Semiconductor Technical Data
MC100ES6014 Rev 3, 06/2005
2.5 V/3.3 V 1:5 Differential ECL/PECL/HSTL/LVDS Clock Driver
The MC100ES6014 is a low skew 1-to-5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL and LVDS inputs can be used when the ES6014 is operating under PECL conditions. The ES6014 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device. To ensure that the tight skew specification is realized, both sides of any differential output need to be terminated identically into 50 even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew. The common enable (EN) is synchronous, outputs are enabled/disabled in the LOW state. This avoids a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input. The MC100ES6014, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the ES6014 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. Single ended CLK input pin operation is limited to a VCC 3.0 V in PECL mode, or VEE -3.0 V in ECL mode. Designers can take advantage of the ES6014's performance to distribute low skew clocks across the backplane or the board. Features * * * * * * * * * 25 ps Within Device Skew 400 ps Typical Propagation Delay Maximum Frequency > 2 GHz Typical The 100 Series Contains Temperature Compensation PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V ECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V LVDS and HSTL Input Compatible Open Input Default State 20-Lead Pb-Free Package Available
MC100ES6014
DT SUFFIX 20-LEAD TSSOP PACKAGE CASE 948E-03
EJ SUFFIX 20-LEAD TSSOP PACKAGE Pb-FREE PACKAGE CASE 948E-03
ORDERING INFORMATION
Device MC100ES6014DT MC100ES6014DTR2 MC100ES6014EJ MC100ES6014EJR2 Package TSSOP-20 TSSOP-20 TSSOP-20 (Pb-Free) TSSOP-20 (Pb-Free)
(c) Freescale Semiconductor, Inc., 2005. All rights reserved.
VCC 20
EN 19
VCC 18
CLK1 17
CLK1 16
VBB 15
CLK0 14
CLK0 CLK_SEL 13 12
VEE 11
1
0
D
Q
1 Q0
2 Q0
3 Q1
4 Q1
5 Q2
6 Q2
7 Q3
8 Q3
9 Q4
10 Q4
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
Figure 1. 20-Lead Pinout (Top View) and Logic Diagram Table 1. Pin Description
Pin CLK0*, CLK0** CLK1*, CLK1** Q0:4, Q0:4 CLK_SEL* EN* VBB VCC VEE Function ECL/PECL/HSTL CLK Input ECL/PECL/HSTL CLK Input ECL/PECL Outputs ECL/PECL Active Clock Select Input ECL Sync Enable Reference Voltage Output Positive Supply Negative Supply
Table 2. Function Table
CLK0 L H X X X CLK1 X X L H X CLK_SEL L L H H X EN L L L L H Q L H L H L*
* On next negative transition of CLK0 or CLK1
* Pins will default LOW when left open. ** Pins will default to VCC/2 when left open.
Table 3. General specifications
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model 0 LFPM, 20 TSSOP 500 LFPM, 20 TSSOP Value 75 k 75 k > 2000 V > 200 V > 1500 V 140C/W 100C/W
Thermal Resistance (Junction-to-Ambient)
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
MC100ES6014 2 Advanced Clock Drivers Device Data Freescale Semiconductor
Table 4. Absolute Maximum Ratings(1)
Symbol VSUPPLY VIN IOUT IBB TA TSTG Characteristic Power Supply Voltage Input Voltage Output Current VBB Sink/Source Current Operating Temperature Range Storage Temperature Range Conditions Difference between VCC & VEE VCC - VEE 3.6 V Continuous Surge Rating 3.9 VCC + 0.3 VEE - 0.3 50 100 0.5 -40 to +85 -65 to +150 Units V V mA mA C C C
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
Table 5. DC Characteristics (VCC = 0 V, VEE = -2.5 V 5% or VCC = 2.5 V 5%, VEE = 0 V)
Symbol IEE VOH VOL VoutPP VIH VIL VBB VPP VCMR IIN Characteristics Power Supply Current Output HIGH Voltage Output LOW Voltage
(1)
-40C Min Typ 30 VCC-1250 200 VCC-1165 VCC-1810 VCC-1400 0.12
(3)
0C to 85C Max 60 VCC-800 VCC-1200 200 VCC-880 VCC-1165 VCC-880 VCC-1475 VCC-1200 1.3 VCC-1.0 150 Min Typ 30 VCC-960 Max 60 VCC-750
Unit mA mV mV mV mV mV mV mV mV A
VCC-990
(1)
VCC-2000 VCC-1550 VCC-1150 VCC-1925 VCC-1630 VCC-1200
Output Peak-to-Peak Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage IBB = 200 A Differential Input Voltage(2) Differential Cross Point Voltage Input Current
VCC-1475 VCC-1810 VCC-1200 VCC-1400 1.3 VCC-1.0 150 0.12 VEE+0.2
VEE+0.2
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification.
Table 6. DC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)
Symbol IEE VOH VOL VoutPP VIH VIL VBB VPP VCMR IIN Characteristics Power Supply Current Output HIGH Voltage Output LOW Voltage
(1) (1)
-40C Min Typ 30 VCC-1150 VCC-1020 200 VCC-1165 VCC-1810 VCC-1400 0.12 VEE+0.2 VCC-880 Max 60 VCC-800 VCC-1200 200 VCC-1165 Min
0C to 85C Typ 30 VCC-970 Max 60 VCC-750
Unit mA mV mV mV
VCC-1950 VCC-1620 VCC-1250 VCC-2000 VCC-1680 VCC-1300 VCC-880 VCC-1475 VCC-1200 1.3 VCC-1.1 150
Output Peak-to-Peak Voltage Input HIGH Voltage Input LOW Voltage Output Reference Voltage IBB = 200 A Differential Input Voltage(2) Differential Cross Point Input Current Voltage(3)
mV mV mV V V A
VCC-1475 VCC-1810 VCC-1200 VCC-1400 1.3 VCC-1.1 150 0.12 VEE+0.2
1. Output termination voltage VTT = 0 V for VCC = 2.5 V operation is supported but the power consumption of the device will increase. 2. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 3. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification.
MC100ES6014 Advanced Clock Drivers Device Data Freescale Semiconductor 3
Table 7. AC Characteristics (VCC = 0 V, VEE = -3.8 V to -3.135 V or VCC = 3.135 V to 3.8 V, VEE = 0 V)(1)
Symbol fmax tPLH tPHL Characteristics Maximum Output Frequency Propagation Delay (Differential) CLK to Q, Q Q, Q RMS (1) 200 VEE+0.2 70 -40C Min 2 300 355 23 425 45 125 1 1200 200 Typ Max Min 2 300 375 23 475 45 175 1 1200 200 25C Typ Max Min 2 300 400 23 525 45 225 1 1200 VCC-1.2 275 85C Typ Max Unit GHz ps ps ps ps mV V ps
tSKEW Within Device Skew(2) Device-to-Device Skew(2) tJITTER Cycle-to-Cycle Jitter VPP
Input Peak-to-Peak Voltage Swing (Differential)
VCMR Differential Cross Point Voltage tr/tf Output Rise/Fall Time (20%-80%)
VCC-1.2 VEE+0.2 225 70
VCC-1.2 VEE+0.2 250 70
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 ohms to VCC-2.0 V. 2. Skew is measured between outputs under identical transitions.
Q Driver Device Q 50 50
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
MC100ES6014 4 Advanced Clock Drivers Device Data Freescale Semiconductor
PACKAGE DIMENSIONS
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CASE 948E-03 ISSUE B 20-LEAD TSSOP PACKAGE
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PACKAGE DIMENSIONS
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MC100ES6014 6 Advanced Clock Drivers Device Data Freescale Semiconductor
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MC100ES6014 Advanced Clock Drivers Device Data Freescale Semiconductor 7
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MC100ES6014 Rev. 3 06/2005

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